1. Field of the Invention
The present invention relates to a data processor which decomposes one instruction into a plurality of internal codes by a decoder for pipelining. More particularly, it relates to a data processor which, when decoding the multi-functional instruction executing plural processings for plural operands by a decoder, decomposes the instruction and outputs as the decoded results, pipelining the decomposed decoded results in respective pipelining stages after the decoding stage of a pipelining mechanism to execute the multi-functional instructions at high efficiency.
2. Description of the Related Art
In a conventional data processor, when processing the multi-functional instructions such as an ENTER instruction for forming a stack frame and saving a register at an entrance of a subroutine in high-level languages, or an EXITD instruction for releasing the stack frame and restoring the register at an exit of the subroutine in high-level languages, or further an LDM instruction which loads plural data from a memory to the registers and an STM instruction which stores plural data from the registers into the memory, these instructions were executed by microprograms so that the instructions were processed by successively executing the necessary processings by the microprogram.
The data processor as stated above which decomposes one instruction into the plural processings by using the microprogram for execution has been known for the long time, for example, it is particularly described in chapter No. 5.5 of "Computer Architecture and Quantitative Approach, " by J. L. Hennessy and D. A. Patterson, Morgan Kaufmann Publishers, Inc. 1990".
The data processor which decomposes the multi-functional instruction into plural processings for execution by the microprogram is disclosed, for example, in the invention disclosed in Japanese Patent Application Laid-Open No. 2-231966(1990).
In the conventional data processor which decomposes the multi-functional instruction into the plural processings by the microprogram for execution as stated above, even in the case of including a pipelining mechanism for the instruction, the multi-functional instruction is processed only in the execution stage, and in a stage where the address calculation of the operand is performed and in a stage where the operand is fetched, processings are not performed at all or hardly any processing is performed.
In the conventional data processor, the multi-functional instruction is processed by decomposing roughly into three stages, preprocessing, actual processing and after-processing by the microprogram in the execution stage. The preprocessing and after-processing among them are not the processings which are designated by the multi-functional instruction but are overheads depending upon hardwares.
Specifically, in the plural data loading instruction for loading plural data to the register from the memory, in accordance with a register list indicated by a bit string of "1" and "0", as preprocessing of data transfer from the memory to the register which is the essential processing of the instruction, the register list outputted from an instruction decoder must be transferred to a priority encoder.
Also in the actual processing, since the operands are accessed while successively calculating addresses of the plural memory operands, complicated controls, such as accessing the preceding operand and calculating the succeeding operand address simultaneously in the instruction executing stage by using an exclusive adder and counter, are executed by the microprogram.
In the conventional data processor, for example, in the case of executing the multi-functional instructions as stated above, since it is necessary to prepare for calculating the operand address and accessing the memory, an extra time is required for such processing in addition to the essential processing, and results in a factor which prevents rapid execution of the multi-functional instructions.